Electronic devices, such as tablets, computers, copiers, digital cameras, smart phones, control systems and automated teller machines, among others, often employ electronic components such as dies that are connected by various interconnect components. The dies may include memory, logic or other integrated circuit (IC) device.
ICs may be implemented to perform specified functions. Example ICs include mask-programmable ICs, such as general purpose ICs, application specific integrated circuits (ASICs), and the like, and field programmable ICs, such as field programmable gate arrays (FPGAs), complex programmable logic devices (CPLDs), and the like.
ICs have become more “dense” over time, i.e., more logic features have been implemented in an IC. More recently, Stacked-Silicon Interconnect Technology (“SSIT”) allows for more than one semiconductor die to be placed in a single package. SSIT ICs may be used to address increased demand for having various ICs within a single package. Conventionally, SSIT products are implemented using an interposer that includes an interposer substrate layer with through-silicon-vias (TSVs) and additional metallization layers built on top of the interposer substrate layer. The interposer provides connectivity between the IC dies and the package substrate. However, fabricating the interposer substrate layer with TSVs for the SSIT products is a complex process. This is due to the several fabrication steps necessary to form the interposer substrate layer with the TSVs that include: forming TSVs within the interposer substrate layer, performing backside thinning and chemical vapor deposition (CVD) or chemical mechanical planarization (CMP), and providing thin wafer handling.
Currently, each product adopting SSIT uses a top cell level design database and photomask to fabricate the interposer wafer. Thus, for each different product, there is additional overhead in terms of engineering time and cost spent to develop the interposer wafer for each product.